Renesas SH7781 - Manual (Page 448)

11. Local Bus State Controller (LBSC)
Rev.1.00 Jan. 10, 2008 Page 418 of 1658
REJ09B0261-0100
Table 11.16 Relationship between Address and CE when Using PCMCIA Interface
Bus (Bits)
Read/
Write
Access
(bits)* 1
Odd/
Even IOIS16 Access CE2 CE1 A0 D15 to D8 D7 to D0
8 Read 8 Even
× ⎯ H
L L Invalid Read data
Odd × ⎯ H L H Invalid Read data
16 Even × First H L L Invalid Lower read data
Even × Second H L H Invalid Upper read data
Odd × ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
Write 8 Even × ⎯ H L L Invalid Write data
Odd × ⎯ H L H Invalid Write data
16 Even × First H L L Invalid Lower write data
Even
×
Second H L H Invalid Upper write data
Odd
× ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
16 Read 8 Even × ⎯ H L L Invalid Read data
Odd × ⎯ L H H Read data Invalid
16 Even × ⎯ L L L Upper read data Lower read data
Odd × ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
Write 8 Even × ⎯ H L L Invalid Write data
Odd × ⎯ L H H Write data Invalid
16 Even × ⎯ L L L Upper write data Lower write data
Odd × ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
Read 8 Even L ⎯ H L L Invalid Read data
Odd L ⎯ L H H Read data Invalid
Dynamic
Bus Sizing* 2
16 Even L
⎯
L L L Upper read data Lower read data
Odd L
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
Write 8 Even L ⎯ H L L Invalid Write data
Odd L ⎯ L H H Write data Invalid
16 Even L ⎯ L L L Upper write data Lower write data
Odd L ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
Read 8 Even H ⎯ H L L Invalid Read data
Odd H First L H H Invalid Invalid
Odd H Second H L L Invalid Read data
16 Even H First L L L Invalid Lower read data
Even H Second H L H Invalid Upper read data
Odd H ⎯ ⎯ ⎯ ⎯ ⎯ ⎯