6 data counter register (fldtcntr) – Renesas SH7781 User Manual
Page 1382
27. NAND Flash Memory Controller (FLCTL)
Rev.1.00 Jan. 10, 2008 Page 1352 of 1658
REJ09B0261-0100
27.3.6
Data Counter Register (FLDTCNTR)
FLDTCNTR is a 32-bit readable/writable register that specifies the number of bytes to be read or
written in command access mode.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
ECFLW[7:0]
DTFLW[7:0]
DTCNT[11:0]
Bit Bit
Name
Initial
Value R/W Description
31 to 24 ECFLW[7:0] H'00
R
FLECFIFO Access Count
Specify the number of longwords (4 bytes) in FLECFIFO
to be read or written. These bit can be used when the
CPU reads from or writes to FLECFIFO.
In reading from FLECFIFO, these bits specify the number
of longwords of the data that can be read from
FLECFIFO.
In writing to FLECFIFO, these bits specify the number of
longwords of empty area that can be written to
FLECFIFO.
23 to 16 DTFLW[7:0] H'00
R
FLDTFIFO Access Count
Specify the number of longwords (4 bytes) in FLDTFIFO
to be read or written. These bit values are used when the
CPU reads from or writes to FLDTFIFO.
In reading from FLDTFIFO, these bits specify the number
of longwords of the data that can be read from
FLDTFIFO.
In writing to FLDTFIFO, these bits specify the number of
longwords of empty area that can be written in
FLDTFIFO.
15 to 12 —
AlI 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
11 to 0
DTCNT[11:0] H'000
R/W Data Count Specification
Specify the number of bytes of data to be read or written
in command access mode (Up to 2048
+ 64 bytes can be
specified.)