Renesas SH7781 - Manual (Page 639)

13. PCI Controller (PCIC)
Rev.1.00 Jan. 10, 2008 Page 609 of 1658
REJ09B0261-0100
(11) PCI Arbiter Interrupt Mask Register (PCIAINTM)
This register is the mask register for PCIAINT.
SH R/W:
PCI R/W:
SH R/W:
PCI R/W:
16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 Bit:
Initial value:
R R R R R R R R R R R R R R R R
R R R R R R R R R R R R R R R R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
— — — — — — — — — — — — — — — —
R/WC R/WC R/WC R/WC R R R R R R R R/WC R/WC R/WC R R
R R R R R R R R R R R R R R R R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
WDP
EIM
RDP
EIM
MAIM TAIM — — — — — — —
MBT
OIM
TBT
OIM
MBIM — —
0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit:
Initial value:
Bit Bit Name
Initial
Value R/W
Description
31 to 14
⎯
All 0 SH: R
PCI: R
Reserved
These bits are always read as 0. The write value
should always be 0.
13 MBIM 0 SH: R/WC
PCI: R
Master-Broken Interrupt Mask
0: MBI disabled (masked)
1: MBI enabled (not masked)
12 TBTOIM 0 SH: R/WC
PCI: R
Target Bus Time-Out Interrupt Mask
0: TBTOI disabled (masked)
1: TBTOI enabled (not masked)
11 MBTOIM 0 SH: R/WC
PCI: R
Master Bus Time-Out Interrupt Mask
0: MBTOI disabled (masked)
1: MBTOI enabled (not masked)
10 to 4
⎯
All 0 SH: R
PCI: R
Reserved
These bits are always read as 0. The write value
should always be 0.
3 TAIM 0 SH: R/WC
PCI: R
Target-Abort Interrupt Mask
0: TAI disabled (masked)
1: TAI enabled (not masked)