Renesas SH7781 - Manual (Page 531)

12. DDR2-SDRAM Interface (DBSC2)
Rev.1.00 Jan. 10, 2008 Page 501 of 1658
REJ09B0261-0100
Bit Bit Name
Initial
Value R/W
Description
12 to 0 TREFI12 to
TREFI0 0 0010
0000 0000 R/W Average Refresh Interval Setting Bits
These bits set the average interval for auto-refresh
operation. Upon refresh execution, this value is added
to the refresh interval count register.
The number of cycles is the number of DDR clock
cycles.
0 0000 0000 0000: Setting prohibited (If specified,
correct operation cannot be
guaranteed.)
:
0 0000 0011 1111: Setting prohibited (If specified,
correct operation cannot be
guaranteed.)
0 0000 0100 0000: 65 cycles
0 0000 0100 0001: 66 cycles
:
1 1111 1111 1111: 8192 cycles
Note: Writing to this register should be performed only when the following condition is met.
• When automatic issue of auto-refresh is disabled (when the ARFEN bit in the
DBRFCNT0 register is cleared to 0.).