Renesas SH7781 - Manual (Page 1063)

21. Serial Communication Interface with FIFO (SCIF)
Rev.1.00 Jan. 10, 2008 Page 1033 of 1658
REJ09B0261-0100
Section 21 Serial Communication Interface with FIFO
(SCIF)
This LSI is equipped with a 6-channel serial communication interface with built-in FIFO buffers
(Serial Communication Interface with FIFO: SCIF). The SCIF can perform both asynchronous and
clocked synchronous serial communications.
64-stage FIFO buffers are provided for transmission and reception, enabling fast, efficient, and
continuous communication.
Channel 0 has modem control functions (
RTS and CTS).
21.1 Features
The SCIF has the following features.
• Asynchronous serial communication mode
Serial data communication is executed using an asynchronous system in which
synchronization is achieved character by character. Serial data communication can be carried
out with standard asynchronous communication chips such as a Universal Asynchronous
Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA).
There is a choice of 8 serial data transfer formats.
⎯ Data length: 7 or 8 bits
⎯ Stop bit length: 1 or 2 bits
⎯ Parity: Even/odd/none
⎯ Receive error detection: Parity, framing, and overrun errors
⎯ Break detection: A break is detected when a framing error lasts for more than 1 frame
length at Space 0 (low level). When a framing error occurs, a break can also be detected by
reading the SCIF0_RXD to SCIF5_RXD pin levels directly from the serial port register
(SCSPTR).
• Clocked synchronous serial communication mode
Serial data communication is synchronized with a clock. Serial data communication can be
carried out with other LSIs that have a synchronous communication function.
There is a single serial data communication format.
Data length: 8 bits
Receive error detection: Overrun errors