Renesas SH7781 - Manual (Page 371)

10. Interrupt Controller (INTC)
Rev.1.00 Jan. 10, 2008 Page 341 of 1658
REJ09B0261-0100
Table 10.15 shows response time. The response time is from the interrupt exception handling to
the start of fetching the first instruction in exception handling routine. In this case, suppose that
the setting values of the following registers that enable or disable interrupt, INTMSK0,
INTMSK1, INTMSK2, INT2MSKR, and INT2GPIC, are changed from the interrupt disable state
to the interrupt enable state.
Table 10.15 Response Time after Changing the Value of Interrupt Enable/Disable Registers
(Interrupt Disabled
→ Interrupt Enabled)
Number of States
IRL IRQ
Peripheral
Modules Remarks
Item INTMSK1 INTMSK2 INTMSK0
INT2MSKR,
INT2GPIC
Registers that
enable/disable
interrupts
Priority determination time* 1Pcyc 8Bcyc +
2Pcyc 1Pcyc 4Pcyc
Wait time until the CPU
finishes the current sequence S-1 (
≥ 0) × Icyc
Interval from the start of
interrupt exception handling
(saving SR and PC) until a
SuperHyway bus request is
issued to fetch the first
instruction of the exception
handling routine 11Icyc
+ 1Scyc
Response
time Total (S + 10) Icyc
+ 1Scyc
+ 1Pcyc (S + 10) Icyc
+ 1Scyc
+ 8Bcyc
+ 2Pcyc (S + 10) Icyc
+ 1Scyc
+ 1Pcyc (S + 10) Icyc
+ 1Scyc
+ 4Pcyc
Legend:
Icyc: Period of one CPU clock cycle
Scyc: Period of one SuperHyway clock cycle
Bcyc: Period of one bus clock cycle
Pcyc: Period of one peripheral clock cycle
S: Number of instruction execution states
Note: * When INTMSKCLR0, INTMSKCLR1, INTMSKCLR2, and INT2MSKCLR are written to,
INTMSK0, INTMSK1, INTMSK2, and INTMSKR enable an interrupt by clearing the
mask bits in INTMSK0, INTMSK1, INTMSK2, and INTMSKR. The priority determination
times in table 10.15 are the values after the values of INTMSK0, INTMSK1, INTMSK2,
and INT2MSKR are changed.