Renesas SH7781 - Manual (Page 1652)

32. Electrical Characteristics
Rev.1.00 Jan. 10, 2008 Page 1622 of 1658
REJ09B0261-0100
32.3.18 Display Unit Signal Timing
Table 32.23 PCICLK/DCLKIN Signal Timing
Conditions: V
DDQ
= 3.3 V ±0.3 V, Ta = -40°C to + 85°C, GND = V
SSQ
= 0 V
Item Symbol Min. Typ. Max. Unit Figure
PCICLK/DCLKIN cycle time t
DICYC
20 — — ns 32.72
PCICLK/DCLKIN high level width t
DCKIH
8 — — ns
PCICLK/DCLKIN low level width t
DCKIL
8 — — ns
Table 32.24 Display Timing
Conditions: V
DDQ
= 3.3 V
±0.3 V, T
a
= –40
°C to +85°C, GND = V
SSQ
= 0 V
Item Symbol Min. Typ. Max. Unit Figures
Display input control
signal setup time t
DS
5 — — ns
Display input control
signal hold time t
DH
3 — — ns
Figure 32.73
(with respect to
PCICLK/
DCLKIN)
DEVSEL/DCLKOUT
output cycle time
t
DCYC
20 — — ns
DEVSEL/DCLKOUT
output high level width
t
DCKH
6 — — ns
Delay time of display
output control signal
output t
DD
-2 — 8 ns
Display digital data output
delay time t
DD
-2 — 8 ns
Figure 32.74
(with respect to
DEVSEL/
DCLKOUT)
IRDY/HSYNC input low
level width
t
EXHLW
4 × t
DCYC
— — ns Figure 32.75
IRDY/HSYNC input high
level width
t
EXHHW
4 × t
DCYC
— — ns
PCIFRAME/VSYNC input
low level width
t
EXVLW
3 × HC — — t
DCYC
LOCK/ODDF setup time 1 t
OD1
(ys + yw) × HC — — t
DCYC
LOCK/ODDF setup time 2 t
OD2
1 × HC — — t
DCYC