Renesas SH7781 - Manual (Page 361)

10. Interrupt Controller (INTC)
Rev.1.00 Jan. 10, 2008 Page 331 of 1658
REJ09B0261-0100
Interrupt Source
INTEVT
Code
Interrupt
Priority
Mask/Clear
Register & Bit
Interrupt
Source
Register
Detail
Source
Register
Priority
within
Sets of
Sources
Default
Priority
IRL[3:0] = HLLL (H'8) H'300
7 INTMSK2[7]
INTMSKCLR2[7]
⎯ ⎯ High High
IRL[7:4] = HLLL (H'8) H'C00
INTMSK2[23]
INTMSKCLR2[23]
⎯ ⎯ Low
IRL[3:0] = HLLH (H'9) H'320
6 INTMSK2[6]
INTMSKCLR2[6]
⎯ ⎯ High
IRL[7:4] = HLLH (H'9) H'C20
INTMSK2[22]
INTMSKCLR2[22]
⎯ ⎯ Low
IRL
L: Low
level
input
H: High
level
input
(See
table
10.11) IRL [3:0] = HLHL (H'A) H'340
5 INTMSK2[5]
INTMSKCLR2[5]
⎯ ⎯ High
IRL[7:4] = HLHL (H'A) H'C40
INTMSK2[21]
INTMSKCLR2[21]
⎯ ⎯ Low
IRL[3:0] = HLHH (H'B) H'360
4 INTMSK2[4]
INTMSKCLR2[4]
⎯ ⎯ High
IRL[7:4] = HLHH (H'B) H'C60
INTMSK2[20]
INTMSKCLR2[20]
⎯ ⎯ Low
IRL[3:0] = HHLL (H'C) H'380
3 INTMSK2[3]
INTMSKCLR2[3]
⎯ ⎯ High
IRL[7:4] = HHLL (H'C) H'C80
INTMSK2[19]
INTMSKCLR2[19]
⎯ ⎯ Low
IRL[3:0] = HHLH (H'D) H'3A0 2
INTMSK2[2]
INTMSKCLR2[2]
⎯ ⎯ High
IRL[7:4] = HHLH (H'D) H'CA0
INTMSK2[18]
INTMSKCLR2[18]
⎯ ⎯ Low
IRL[3:0] = HHHL (H'E) H'3C0 1
INTMSK2[1]
INTMSKCLR2[1]
⎯ ⎯ High
IRL[7:4] = HHHL (H'E) H'CC0
INTMSK2[17]
INTMSKCLR2[17]
⎯ ⎯ Low
Low