Renesas SH7781 - Manual (Page 716)

14. Direct Memory Access Controller (DMAC)
Rev.1.00 Jan. 10, 2008 Page 686 of 1658
REJ09B0261-0100
Bit Bit Name
Initial
Value R/W Descriptions
15, 14 DM[1:0] 00 R/W Destination Address Mode 1, 0
Specify whether the DMA destination address is
incremented or decremented.
00: Destination address is fixed
01: Destination address is incremented
byte unit transfer:
+1
word unit transfer:
+2
longword unit transfer:
+4
16-byte unit transfer:
+16
32-byte unit transfer:
+32
10: Destination address is decremented
byte unit transfer:
−1
word unit transfer:
−2
longword unit transfer:
−4
Setting prohibited in 16/32-byte unit transfer
11: Setting prohibited
For any setting (00, 01, or 10), specifying a transfer size
greater than the bus width divides bus cycles into two or
more, and increases the number of addresses for the
divided bus cycles.
13, 12 SM[1:0] 00 R/W Source Address Mode 1, 0
Specify whether the DMA source address is
incremented or decremented.
00: Source address is fixed
01: Source address is incremented
byte unit transfer:
+1
word unit transfer:
+2
longword units transfer:
+4
16-byte unit transfer:
+16
32-byte unit transfer:
+32
10: Source address is decremented
byte unit transfer:
−1
word unit transfer:
−2
longword unit transfer:
−4
Setting prohibited in 16/32-byte unit transfer
11: Setting prohibited
For any setting (00, 01, or 10), specifying a transfer size
greater than the bus width divides bus cycles into two or
more, and increases the number of addresses for the
divided bus cycles.