2 standby control register 0 (mstpcr0) – Renesas SH7781 User Manual
Page 816
17. Power-Down Mode
Rev.1.00 Jan. 10, 2008 Page 786 of 1658
REJ09B0261-0100
17.3.2
Standby Control Register 0 (MSTPCR0)
MSTPCR0 is a 32-bit readable/writable register that can specify whether each peripheral module
operates or is stopped. MSTPCR can be accessed only in longword.
This register is initialized by a power-on reset by the
PRESET pin or power-on reset by WDT
overflow, or H-UDI reset.
16
17
18
19
20
21
22
23
24
25
26
27
28
29
31
30
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MSTP[17:16]
⎯
⎯
MSTP[21:20]
⎯
⎯
MSTP[29:24]
⎯
⎯
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
BIt:
Initial value:
R/W:
0
1
2
3
4
5
6
7
8
9
10
11
12
13
15
14
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
⎯
⎯
MSTP[3:2]
⎯
⎯
⎯
⎯
MSTP[9:8]
⎯
⎯
MSTP[13:12]
⎯
⎯
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
BIt:
Initial value:
R/W:
Bit Bit
Name
Initial
Value R/W
Description
31, 30
⎯ All
0
R/W
Reserved
These bits are always read as 0. The write value
should always be 0.
29 to 24 MSTP[29:24]
All 0
R/W
Module Stop Bit [29:24]
Specify that the clock supply to the module of the
corresponding bit is stopped
[29]: SCIF channel 5, [28]: SCIF channel 4,
[27]: SCIF channel 3, [26]: SCIF channel 2,
[25]: SCIF channel 1, [24]: SCIF channel 0
0: The corresponding module operates
1: The clock to the corresponding module is
stopped
23, 22
⎯ All
0
R/W
Reserved
These bits are always read as 0. The write value
should always be 0.