Renesas SH7781 - Manual (Page 1658)

Appendix
Rev.1.00 Jan. 10, 2008 Page 1628 of 1658
REJ09B0261-0100
B. Mode Pin Settings
The MODE14–MODE0 pin values are input in the event of a power-on reset via the
PRESET pin.
Note: The MODE6 pin is output state after power-on reset.
Legend:
H: High level input
L: Low level input
Table B.1 Clock Operating Modes with External Pin Combination
Pin Value
MODE [4:0]
Pin Number
OSC/
External
input
Frequency
[MHz]
Frequency
(vs. Input Clock)
Clock
Operating
Mode
4 3 2 1 0 Min Max
Divider
1 PLL
1
Ick Uck SHck GAck DUck Pck DDRck Bck
0 L L L L L Ч 36 Ч 18 Ч 18 Ч 9 Ч 9 Ч 3 Ч 18 Ч 6
1 L L L L H Ч 36 Ч 18 Ч 18 Ч 9 Ч 9 Ч 3/2 Ч 18 Ч 3/2
2 L L L H L Ч 36 Ч 12 Ч 12 Ч 6 Ч 6 Ч 3 Ч 12 Ч 6
3 L L L H H
12 17
Ч 1
Ч 36 Ч 12 Ч 12 Ч 6 Ч 6 Ч 3/2 Ч 12 Ч 3/2
16 H L L L L 23 34
Ч 1 Ч 36 Ч 18 Ч 9 Ч 9 Ч 9/2 Ч 9/2 Ч 3/2 Ч 9 Ч 3
17 H L L L H Ч 18 Ч 9 Ч 9 Ч 9/2 Ч 9/2 Ч 3/4 Ч 9 Ч 3/4
18 H L L H L Ч 18 Ч 6 Ч 6 Ч 3 Ч 3 Ч 3/2 Ч 6 Ч 3
19 H L L H H Ч 18 Ч 6 Ч 6 Ч 3 Ч 3 Ч 3/4 Ч 6 Ч 3/4
Note: When MODE12 or MODE11 is set to low level, DUck is stopped.
The division ratio of the divider 2 can be read out from FRQMR1.
For details, see section 15, Clock Pulse Generator (CPG).