Renesas SH7781 - Manual (Page 107)

4. Pipelining
Rev.1.00 Jan. 10, 2008 Page 77 of 1658
REJ09B0261-0100
Instruction
Group Instruction
FE FADD
FSUB
FCMP (S/D)
FCNVDS
FCNVSD
FDIV
FIPR
FLOAT
FMAC
FMUL
FRCHG
FSCHG
FSQRT
FTRC
FTRV
FSCA
FSRRA
FPCHG
CO AND.B #imm,@(R0,GBR)
ICBI
LDC Rm,DBR
LDC Rm, SGR
LDC Rm,SR
LDC.L @Rm+,DBR
LDC.L @Rm+,SGR
LDC.L @Rm+,SR
LDTLB
MAC.L
MAC.W
MOVCO
MOVLI
OR.B #imm,@(R0,GBR)
PREFI
RTE
SLEEP
STC SR,Rn
STC.L SR,@-Rn
SYNCO
TAS.B
TRAPA
TST.B #imm,@(R0,GBR)
XOR.B #imm,@(R0,GBR)
Legend:
R: Rm/Rn
@adr: Address
SR1: MACH/MACL/PR
SR2: FPUL/FPSCR
CR1: GBR/Rp_BANK/SPC/SSR/VBR
CR2: CR1/DBR/SGR
FR: FRm/FRn/DRm/DRn/XDm/XDn
The parallel execution of two instructions can be carried out under following conditions.
1. Both addr (preceding instruction) and addr
+2 (following instruction) are specified within the
minimum page size (1 Kbyte).
2. The execution of these two instructions is supported in table 4.3, Combination of Preceding
and Following Instructions.
3. Data used by an instruction of addr does not conflict with data used by a previous instruction
4. Data used by an instruction of addr
+2 does not conflict with data used by a previous
instruction
5. Both instructions are valid