Renesas SH7781 - Manual (Page 733)

14. Direct Memory Access Controller (DMAC)
Rev.1.00 Jan. 10, 2008 Page 703 of 1658
REJ09B0261-0100
(3) On-Chip Peripheral Module Request Mode
On-chip peripheral module request mode is a mode that performs transfer by DMA transfer
request signal from an on-chip peripheral module. DMA transfer request signals include a transmit
data empty transfer request and receive data full transfer request that are from the SCIF0 to SCIF5,
HAC0, HAC1, HSPI, SIOF, SSI0, SSI1, and MMCIF set in DMARS0 to DMARS5, and a transfer
request from the FLCTL.
If the DMA transfer is enabled (DE = 1, DME = 1, TE = 0, AE = 0, NMIF = 0) in this mode, a
transfer is performed by transfer request signal.
When a transmit data empty transfer request of the SCIF0 is specified as the transfer request, the
transfer destination must be the SCIF0's transmit data register. Likewise, when receive data full
transfer request of the SCIF0 is specified as the transfer request, the transfer source must be the
SCIF0's receive data register. These conditions also apply to the SCIF1 to SCIF5, HAC0, HAC1,
HSPI, SIOF, SSI0, SSI1 and MMCIF.
Table 14.8 shows the settings required to select the on-chip peripheral module request mode.