11 transmit data assign register (sitdar) – Renesas SH7781 User Manual
Page 1153
22. Serial I/O with FIFO (SIOF)
Rev.1.00 Jan. 10, 2008 Page 1123 of 1658
REJ09B0261-0100
Bit Bit
Name
Initial
Value R/W Description
2 to 0
BRDV[2:0]
000
R/W
Baud Rate Generator's Division Ratio Setting
These bits set the frequency division ratio for the output
stage of the baud rate generator.
000: Prescaler output
× 1/2
001: Prescaler output
× 1/4
010: Prescaler output
× 1/8
011: Prescaler output
× 1/16
100: Prescaler output
× 1/32
101: Setting prohibited
110: Setting prohibited
111: Prescaler output
× 1/1*
Note: This setting is valid only when the bits BRPS4 to
BRPS0 are set to B'00001.
22.3.11
Transmit Data Assign Register (SITDAR)
SITDAR is a 16-bit readable/writable register that specifies the position of the transmit data in a
frame.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
15
14
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TDRA[3:0]
—
—
TLREP
TDRE
TDLA[3:0]
—
TDLE
—
R/W
R/W
R/W
R/W
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R/W
R
BIt:
Initial value:
R/W:
—
Bit Bit
Name
Initial
Value R/W Description
15
TDLE
0
R/W
Transmit Left-Channel Data Enable
0: Disables left-channel data transmission
1: Enables left-channel data transmission
14 to 12
⎯ All
0
R
Reserved
These bits are always read as 0. The write value should
always be 0.