Renesas SH7781 - Manual (Page 1392)

27. NAND Flash Memory Controller (FLCTL)
Rev.1.00 Jan. 10, 2008 Page 1362 of 1658
REJ09B0261-0100
27.3.12 Control Code FIFO Register (FLECFIFO)
FLECFIFO is used to read from or write to the control code FIFO area.
The read and write directions specified by the SELRW bit in FLCMDCR must match the read and
write access directions specified in this register.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
ECFO[31:24] ECFO[23:16]
ECFO[15:8] ECFO[7:0]
— — — — — — — — — — — — — — — —
— — — — — — — — — — — — — — — —
Bit Bit Name
Initial
Value R/W
Description
31 to 24 ECFO[31:24] Undefined R/W First Data
Specify the first data to be input or output via the FD7 to
FD0 pins.
In writing: Specify write data
In reading: Store read data
23 to 16 ECFO[23:16] Undefined R/W Second Data
Specify the second data to be input or output via the
FD7 to FD0 pins.
In writing: Specify write data
In reading: Store read data
15 to 8 ECFO[15:8] Undefined R/W Third Data
Specify the third data to be input or output via the FD7
to FD0 pins.
In writing: Specify write data
In reading: Store read data
7 to 0 ECFO[7:0] Undefined R/W Fourth Data
Specify the fourth data to be input or output via the FD7
to FD0 pins.
In writing: Specify write data
In reading: Store read data