Renesas SH7781 - Manual (Page 239)

7. Memory Management Unit (MMU)
Rev.1.00 Jan. 10, 2008 Page 209 of 1658
REJ09B0261-0100
7.10 Usage Notes
7.10.1 Note on Using LDTLB Instruction
When using an LDTLB instruction instead of software to a value to the MMUCR. URC, execute 1
or 2 below.
1. In 29-bit address mode, follow A. and B. below. In 32-bit address mode, follow A. through D.
below.
A. Place the TLB miss exception handling routine* 1 only in the P1, P2 area ,or the on-chip
memory so that all the instruction accesses* 3 in the TLB miss exception handling routine
should occur solely in the P1, P2 area, or the on-chip memory. Clear the RP bit in the
RAMCR register to 0 (initial value), when the TLB miss exception handling routine is
placed in the on-chip memory.
B. Use only one page of the PMB for instruction accesses* 3 in the TLB miss exception
handling routine* 1 . In 32-bit address mode, do not place them in the last 64 bytes of a page
of the PMB.
C. In 32-bit address mode, obey 1 and 2 below when recording information in the UTLB in
the MMU-related exception* 2 handling routine.
a. When thea TLB miss exception occurs, and recording the information of a page with
the access right in the UTLB, do not record the page, in which the exception has
occurred, in the UTLB using the following two operations.
⎯ Specifies the protection key data that causes a protection violation exception upon
re-execution of the instruction that has caused the TLB miss exception and records
the page, in which the TLB miss exception has occurred, in the UTLB.
⎯ Specifies the protection key data that does not cause a protection violation
exception in the protection violation exception handling routine to record the page
in the UTLB and re-executes the instruction that has caused the protection violation
exception.
b. When an initial page write exception occurs and the TLB entry in the UTLB of which
the dirty bit is 1 is replaced, before the write instruction for the page corresponding to
this replaced TLB entry is completed, register the TLB entry of which the dirty bit is 1.
D. Do not make an attempt to execute the FDIV or FSQRT instruction in the TLB miss
exception handling routine.
2. If a TLB miss exception occurs, add 1 to MMUCR.URC before executing an LDTLB
instruction.