Renesas SH7781 - Manual (Page 1562)

31. Register List
Rev.1.00 Jan. 10, 2008 Page 1532 of 1658
REJ09B0261-0100
Module
Name Name Abbreviation R/W
P4 Area
Address
Area 7
Address
Access
Size
GPIO Port N pull-up control register PNPUPR R/W H'FFE7 0058 H'1FE7 0058 8
Input pin pull-up control register 1 PPUPR1 R/W H'FFE7 0060 H'1FE7 0060 16
Input pin pull-up control register 2 PPUPR2 R/W H'FFE7 0062 H'1FE7 0062 16
Peripheral module select register 1 P1MSELR R/W H'FFE7 0080 H'1FE7 0080 16
Peripheral module select register 2 P2MSELR R/W H'FFE7 0082 H'1FE7 0082 16
UBC Match condition setting register 0 CBR0 R/W H'FF200000 H'1F200000 32
Match operation setting register 0 CRR0 R/W H'FF200004 H'1F200004 32
Match address setting register 0 CAR0 R/W H'FF200008 H'1F200008 32
Match address mask setting register 0 CAMR0 R/W H'FF20000C H'1F20000C 32
Match condition setting register 1 CBR1 R/W H'FF200020 H'1F200020 32
Match operation setting register 1 CRR1 R/W H'FF200024 H'1F200024 32
Match address setting register 1 CAR1 R/W H'FF200028 H'1F200028 32
Match address mask setting register 1 CAMR1 R/W H'FF20002C H'1F20002C 32
Match data setting register 1 CDR1 R/W H'FF200030 H'1F200030 32
Match data mask setting register 1 CDMR1 R/W H'FF200034 H'1F200034 32
Execution count break register 1 CETR1 R/W H'FF200038 H'1F200038 32
Channel match flag register CCMFR R/W H'FF200600 H'1F200600 32
Break control register CBCR R/W H'FF200620 H'1F200620 32
H-UDI Instruction register SDIR R H'FC11 0000 H'1C11 0000 16
Interrupt source register SDINT R/W H'FC11 0018 H'1C11 0018 16
Boundary scan register SDBSR ⎯ ⎯ ⎯ ⎯
Bypass register SDBPR ⎯ ⎯ ⎯ ⎯
Notes: 1. The interrupt source registers (INTREQ) are readable and conditionally writable
registers. For details, refer to section 10.3.1 (4), Interrupt Source Register (INTREQ).
2. The NMI flag control register (NMIFCR) is readable and conditionally writable register.
For details, refer to section 10.3.1 (11), NMI Flag Control Register (NMIFCR).
3. To clear the flag, the HE and TE bits in CHCR can be read as 1, and then, 0 can be
written to.
4. To clear the flag, the AE and NMIF bits in DMAOR can be read as 1, and then, 0 can be
written to.
5. To clear a flag, only writing 0 to bits 7 to 4, 1, and 0 is valid.
6. To clear a flag, only writing 0 to bit 0 is valid.