Renesas SH7781 - Manual (Page 1193)

23. Serial Peripheral Interface (HSPI)
Rev.1.00 Jan. 10, 2008 Page 1163 of 1658
REJ09B0261-0100
Bit Bit Name
Initial
Value R/W Description
2 RXDE 0 R/W Receive DMA Enable
0: Receive DMA transfer request disabled
1: Receive DMA transfer request enabled
1 TXDE 0 R/W Transmit DMA Enable
0: Transmit DMA transfer request disabled
1: Transmit DMA transfer request enabled
0 MASL 0 R/W Master/Slave Select Bit
0: HSPI module configured as a slave
1: HSPI module configured as a master
23.3.4 Transmit Buffer Register (SPTBR)
SPTBR is a 32-bit readable/writable register that stores data to be transmitted.
16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30
— — — — — — — — — — — — — — — —
R R R R R R R R R R R R R R R R
Bit:
Initial value:
R/W:
0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14
0 0 0 0 0 0 0 0
TD — — — — — — — —
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R R R
Bit:
Initial value:
R/W:
Bit Bit Name
Initial
Value R/W Description
31 to 8
⎯ All
0 R Reserved
These bits are always read as an undefined value. The
write value should always be 0.
7 to 0 TD All 0 R/W Transmit Data
Data written to this register is transferred to the shift
register for transmission.
When reading these bits, the data stored in the transmit
buffer is always read.