Cbr1 – Renesas SH7781 User Manual
Page 1490
29. User Break Controller (UBC)
Rev.1.00 Jan. 10, 2008 Page 1460 of 1658
REJ09B0261-0100
• CBR1
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
MFE
AIE
MFI
AIV
DBE
SZ
ETBE
CD
ID
RW
CE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R
R
R
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
Bit :
Initial value :
R/W:
Bit :
Initial value :
R/W:
Bit Bit
Name
Initial
Value R/W
Description
31
MFE
0
R/W
Match Flag Enable
Specifies whether or not to include the match flag value
specified by the MFI bit of this register in the match
conditions. When the specified match flag value is 1,
the condition is determined to be satisfied.
0: The match flag is not included in the match
conditions; thus, not checked.
1: The match flag is included in the match conditions.
30
AIE 0
R/W
ASID
Enable
Specifies whether or not to include the ASID specified
by the AIV bit of this register in the match conditions.
0: The ASID is not included in the match conditions;
thus, not checked.
1: The ASID is included in the match conditions.
29 to 24 MFI
100000
R/W
Match Flag Specify
Specifies the match flag to be included in the match
conditions.
000000: The MF0 bit of the CCMFR register
000001: The MF1 bit of the CCMFR register
Others: Reserved (setting prohibited)
Note: The initial value is the reserved value, but when 1
is written into CBR1[0], MFI must be set to
000000 or 000001. And note that the channel 1 is
not hit when MFE bit of this register is 1 and MFI
bits are 000001 in the condition of CCRMF.MF1 =
0.