Renesas SH7781 - Manual (Page 749)

14. Direct Memory Access Controller (DMAC)
Rev.1.00 Jan. 10, 2008 Page 719 of 1658
REJ09B0261-0100
14.4.5 Repeat Mode Transfer
A repeat mode transfer of the DMAC enables a DMA transfer to repeat without specifying the
transfer settings before a transfer.
Using a repeat mode transfer with the half end function can execute a double buffer transfer
virtually. This function can execute the following procedures efficiently. As an example, the
operation in receiving voice data from the VOICE CODEC and compressing the data is described.
The process described supposes that processing of compressing is executed whenever 40-word
voice data is received. Suppose that voice data is received by SIOF.
1. DMAC settings
⎯ Set the address of the SIOF receive data register in SAR
⎯ Set the address of an internal memory data store area in DAR
⎯ Set TCR to H'50 (80 times)
⎯ Set the following values to CHCR
RPT (bits 27 to 25) = B'010: Repeat mode (use DAR as a repeat area)
HIE (bit 18) = B'1: TCR/2 interrupt generated
DM (bits 15 and 14) = B'01: DAR incremented
SM (bits 13 and 12) = B'00: SAR fixed
IE (bit 2) = B'1: Interrupt enabled
DE (bit 0) = B'1: DMA transfer enabled
Set bits such as bits TB and TS according to use conditions
⎯ Set bits CMS and PR in DMAOR according to use conditions and set the DME bit to 1
2. Voice data is received and transferred by SIOF/DMAC
3. TCR is decreased to half of the initial value and an interrupt is generated
After reading CHCR and confirming that the HE (bit 19) is set to 1 by an interrupt processing,
clear HE (bit 19) to 0 and compress 40-word voice data from the address set in DAR.
4. TCR is cleared to 0 and an interrupt is generated
After reading CHCR and confirming that the TE bit is set to 1 with an interrupt processing,
clear the TE bit to 0 and compress 40-word voice data from the address that is obtained by
adding 40 to the address set in DAR. After this operation, the value of DARB is copied to
DAR in DMAC and initialized, and the value of TCRB is copied to TCR and initialized to
H'50 (80 times).
5. Steps 2 to 4 are repeated until the DME or DE bit is set to B'0, or an NMI interrupt is
generated. (If the HE bit is not cleared to 0 in the procedure 2 or if the TE bit is not cleared to 0
in the procedure 4, the transfer is stopped when both the HE and TE bits are set to 1.)