Renesas SH7781 - Manual (Page 1007)

20. Graphics Data Translation Accelerator (GDTA)
Rev.1.00 Jan. 10, 2008 Page 977 of 1658
REJ09B0261-0100
Table 20.4 GDTA Register States in Each Processing Mode (GDTA Common Registers)
Register
Abbreviation Power-On
Reset Manual Reset Sleep Deep Sleep
GACMR H'0000 0000 H'0000 0000 Retained Retained
GACER H'0000 0000 H'0000 0000 Retained Retained
GACISR H'0000 0000 H'0000 0000 Retained Retained
GACICR H'0000 0000 H'0000 0000 Retained Retained
GACIER H'0000 0000 H'0000 0000 Retained Retained
DWCL_CTL H'0000 0000 H'0000 0000 Retained Retained
DRCL_CTL H'0000 0000 H'0000 0000 Retained Retained
DRMC_CTL H'0000 0000 H'0000 0000 Retained Retained
DWMC_CTL H'0000 0000 H'0000 0000 Retained Retained
DCP_CTL H'0000 0000 H'0000 0000 Retained Retained
DID_CTL H'0000 0000 H'0000 0000 Retained Retained
Table 20.5 GDTA States in Each Processing Mode (CL Block)
Register
Abbreviation Power-On
Reset Manual Reset Sleep Deep Sleep
CLCF H'0000 0000 H'0000 0000 Retained H'0000_0000
CLCR H'0000 0000 H'0000 0000 Retained Retained
CLSR H'0000 0000 H'0000 0000 Retained Retained
CLWR H'0000 0000 H'0000 0000 Retained Retained
CLHR H'0000 0000 H'0000 0000 Retained Retained
CLIYPR H'0000 0000 H'0000 0000 Retained Retained
CLIUVPR H'0000 0000 H'0000 0000 Retained Retained
CLOPR H'0000 0000 H'0000 0000 Retained Retained
CLPLPR H'0000 0000 H'0000 0000 Retained Retained
Note: A 0 is always read from these registers.