Renesas SH7781 - Manual (Page 569)

12. DDR2-SDRAM Interface (DBSC2)
Rev.1.00 Jan. 10, 2008 Page 539 of 1658
REJ09B0261-0100
MCK0,
MCK1
MA[14:11]
MA[9:0]
MBA[2:0]
MCKE
MCS
MRAS
MCAS
MWE
MA[10]
bank A
Invalid
MDQS[3:0]
MDQ[31:0]
MDM[3:0] Invalid
Invalid
Invalid
Invalid
PRE
bank A
Invalid
Invalid
Invalid
Invalid
SDRAM
command ACT
bank A
Valid
Valid
Valid
Invalid
Invalid
Invalid
WRITE
bank A
Example of CL = 3
WRITE
Write data
tWR
= 3 cycles
Valid
Valid
Valid
Valid
Valid
Valid
Valid
High level
Figure 12.16 tWR
Figure 12.16 shows a case in which, after a write request, access occurs requiring that bank B be
closed. After the issue of a WRITE command, it is necessary to wait for time tWR or longer after
output of the write data before issuing a PRE command.