Renesas SH7781 - Manual (Page 1178)

22. Serial I/O with FIFO (SIOF)
Rev.1.00 Jan. 10, 2008 Page 1148 of 1658
REJ09B0261-0100
(4) 16-bit Stereo Data (1)
L/R method, rising edge sampling, slot No.0 used for left-channel data, slot No.1 used for right-
channel data, and frame length = 32 bits
TRMD[1:0] = 11,
TDLE = 1,
RDLE = 1,
CD0E = 0, REDG = 1,
TDLA[3:0] = 0000,
RDLA[3:0] = 0000,
CD0A[3:0] = 0000, FL[3:0] = 1101 (frame length: 32 bits)
TDRE = 1,
RDRE = 1,
CD1E = 0,
TDRA[3:0] = 0001,
RDRA[3:0] = 0001,
CD1A[3:0] = 0000
Slot No.0 Slot No.1
Specifications:
1 frame
No bit delay
SIOF_SCK
SIOF_RXD
SIOF_TXD
SIOF_SYNC
L-channel data R-channel data
Figure 22.16 Transmit and Receive Timing (16-Bit Stereo Data (1))
(5)
16-bit Stereo Data (2)
L/R method, rising edge sampling, slot No.0 used for left-channel transmit data, slot No.1 used for
left-channel receive data, slot No.2 used for right-channel transmit data, slot No.3 used for right-
channel receive data, and frame length = 64 bits
TRMD[1:0] = 11,
TDLE = 1,
RDLE = 1,
CD0E = 0, REDG = 1,
TDLA[3:0] = 0000,
RDLA[3:0] = 0001,
CD0A[3:0] = 0000, FL[3:0] = 1101 (frame length: 64 bits),
TDRE = 1,
RDRE = 1,
CD1E = 0,
TDRA[3:0] = 0010,
RDRA[3:0] = 0011,
CD1A[3:0] = 0000
Slot No.0 Slot No.1 Slot No.2 Slot No.3
Specifications:
1 frame
No bit delay
SIOF_SCK
SIOF_RXD
SIOF_TXD
SIOF_SYNC
R-channel data L-channel data
L-channel data R-channel data
Figure 22.17 Transmit and Receive Timing (16-Bit Stereo Data (2))