Renesas SH7781 - Manual (Page 437)

11. Local Bus State Controller (LBSC)
Rev.1.00 Jan. 10, 2008 Page 407 of 1658
REJ09B0261-0100
A16
A0
CSn
RD
D7
D0
WE0
SH7785
128K × 8 bits
SRAM
A16
A0
CS
OE
I/O7
I/O0
WE
•••• ••••
•••• ••••
•••• ••••
•••• ••••
Figure 11.8 Example of 8-Bit Data Width SRAM Connection
(2) Wait Cycle Control
Wait cycle insertion for the SRAM interface can be controlled by CSnWCR. If the IW bits in
CSnWCR are set to a value other than 0, a software wait is inserted in accordance with the wait
control bits. For details, see section 11.4.4, CSn Wait Control Register (CSnWCR).
The specified number of Tw cycles is inserted as wait cycles in accordance with the CSnWCR
setting. The wait cycle insertion timing is shown in figure 11.9.