Renesas SH7781 - Manual (Page 120)

5. Exception Handling
Rev.1.00 Jan. 10, 2008 Page 90 of 1658
REJ09B0261-0100
Table 5.2 States of Register in Each Operating Mode
Register Name Abbr.
Power-on
Reset
Manual Reset Sleep Standby
TRAPA exception register TRA Undefined Undefined Retained Retained
Exception event register EXPEVT H'0000 0000 H'0000 0020 Retained Retained
Interrupt event register INTEVT Undefined Undefined Retained Retained
Non-support detection exception
register EXPMASK H'0000 0013 H'0000 0013 Retained Retained
5.2.1 TRAPA Exception Register (TRA)
The TRAPA exception register (TRA) consists of 8-bit immediate data (imm) for the TRAPA
instruction. TRA is set automatically by hardware when a TRAPA instruction is executed. TRA
can also be modified by software.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit:
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0
Initial value:
R R R R R R R R R R R R R R R R
R/W R/W R/W
TRACODE
R/W R/W R/W R R
R/W:
Bit:
Initial value:
R/W:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0
R R R R R R R/W R/W
Bit Bit Name Initial Value R/W Description
31 to 10
⎯ All
0 R Reserved
For details on reading/writing this bit, see General
Precautions on Handling of Product.
9 to 2 TRACODE Undefined R/W TRAPA Code
8-bit immediate data of TRAPA instruction is set
1, 0
⎯ All
0 R Reserved
For details on reading/writing this bit, see General
Precautions on Handling of Product.