Renesas SH7781 User Manual

Page 712

14. Direct Memory Access Controller (DMAC)

Rev.1.00 Jan. 10, 2008 Page 682 of 1658
REJ09B0261-0100

Bit Bit

Name

Initial
Value R/W Descriptions

27 to 25 RPT[2:0]

000

R/W

DMA Setting Update Specification

These bits are valid in only CHCR0 to CHCR3, and
CHCR6 to CHCR9.

000: Normal mode

001: Repeat mode

SAR/DAR/TCR are repeated

010: Repeat mode

DAR/TCR is repeated

011: Repeat mode

SAR/TCR is repeated

100: Reserved (setting prohibited)

101: Reload mode

SAR/DAR is reloaded

110: Reload mode

DAR is reloaded

111: Reload mode

SAR is reloaded

⎯ 0 R

Reserved

This bit is always read as 0. The write value should
always be 0.

23 DO 0 R/W

DMA

Overrun

Selects whether DREQ is detected by overrun 0 or by
overrun 1. This bit is valid in only CHCR0 to CHCR3.

0: Detects DREQ by overrun 0

1: Detects DREQ by overrun 1

R/W

Request Check Level

Selects whether the DRAK signal output is an active-
high or active-low. This bit valid in only CHCR0 to
CHCR3. If the DRAK active direction is changed,
reflecting the change on the external pins requires one
cycle of the external bus clock after writing to the
register is completed.

0: DRAK is an active-low output

1: DRAK is an active-high output