Renesas SH7781 - Manual (Page 349)

10. Interrupt Controller (INTC)
Rev.1.00 Jan. 10, 2008 Page 319 of 1658
REJ09B0261-0100
(5) INT2B4: Detailed Interrupt Sources for the MMCIF
Module Bit Name Detailed Source Description
MMCIF 31 to 4
⎯ Reserved
These bits are read as 0
and cannot be modified.
3 FRDY FIFO ready end interrupt
2 ERR CRC error interrupt, data
timeout error interrupt,
or command timeout
error interrupt
MMCIF interrupt sources are
indicated. This register indicates the
MMCIF interrupt sources even if the
mask setting for MMCIF is made in
the interrupt mask register.
1 TRAN Data response interrupt,
data transfer end
interrupt, command
response receive end
interrupt, command
transmit end interrupt, or
data busy end interrupt
0 FSTAT FIFO empty interrupt or
FIFO full interrupt
(6) INT2B5: Detailed Interrupt Sources for the FLCTL
Module Bit Name Detailed Source Description
FLCTL 31 to 4
⎯ Reserved
These bits are read as
0 and cannot be
modified.
3 FLTRQ1 FLCTL FLECFIFO
transfer request
interrupt
2 FLTRQ0 FLCTL TLDTFIFO
transfer request
interrupt
FLCTL interrupt sources are
indicated. This register indicates the
FLCTL interrupt sources even if the
mask setting for FLCTL is made in
the interrupt mask register.
1 FLTEND FLCTL transfer end
interrupt
0 FLSTE FLCTL status error
interrupt or ready/busy
timeout error interrupt