Renesas SH7781 - Manual (Page 366)

10. Interrupt Controller (INTC)
Rev.1.00 Jan. 10, 2008 Page 336 of 1658
REJ09B0261-0100
Interrupt Source
INTEVT
Code
Interrupt
Priority
Mask/Clear
Register & Bit
Interrupt
Source
Register
Detail
Source
Register
Priority
within
Sets of
Sources
Default
Priority
HAC-ch1 HACI1 H'EE0 INT2PRI6
[20:16]
INT2MSKR[13]
INT2MSKCLR
[13]
INT2A0[13]
INT2A1[13]
⎯
FLCTL FLSTE* H'F00 INT2B5[0] High
High
FLTEND* H'F20
INT2PRI8
[28:24]
INT2MSKR[23]
INT2MSKCR[23]
INT2A0[23]
INT2A1[23]
INT2B5[1]
FLTRQ0* H'F40 INT2B5[2]
FLTRQ1* H'F60 INT2B5[3] Low
GPIO GPIOI0 (Port E0) H'F80 INT2B6[0] High
GPIOI0 (Port E1)
INT2MSKR[24]
INT2MSKCR[24]
INT2A0[24]
INT2A1[24]
INT2B6[1]
GPIOI0 (Port E2)
INT2PRI8
[20:16]
INT2B6[2]
GPIOI1 (Port E3) H'FA0 INT2B6[8]
GPIOI1 (Port E4) INT2B6[9]
GPIOI1 (Port E5) INT2B6[10]
GPIOI2 (Port H1) H'FC0 INT2B6[16]
GPIOI2 (Port H2) INT2B6[17]
GPIOI2 (Port H3) INT2B6[18]
GPIOI2 (Port H4) INT2B6[19]
GPIOI3 (Port L6) H'FE0 INT2B6[24]
GPIOI3 (Port L7) INT2B6[25] Low Low
Note: * ITI: Interval timer interrupt
TUNI0 to TUNI5: TMU channels 0 to 5 under flow interrupt
TICPI2: TMU channel 2 input capture interrupt
DMINT0 to DMINT11: Transfer end or half-end interrupts for DMAC channel 0 to 11
DMAE0: DMAC address error interrupt (channels 0 to 5)
DMAE1: DMAC address error interrupt (channels 6 to 11)
ERI0, ERI1, ERI2, ERI3, ERI4, ERI5: SCIF channels 0 to 5 receive error interrupts
RXI0, RXI1, RXI2, RXI3, RXI4, RXI5: SCIF channels 0 to 5 receive data full interrupts
BRI0, BRI1, BRI2, BRI3, BRI4, BRI5: SCIF channels 0 to 5 break interrupts
TXI0, TXI1, TXI2, TXI3, TXI4, TXI5: SCIF channels 0 to 5 transmission data empty
interrupts
FLSTE: FLCTL error interrupt
FLTEND: FLCTL error interrupt
FLTRQ0: FLCTL data FIFO transfer request interrupt
FLTRQ1: FLCTL control code FIFO transfer request interrupt