Renesas SH7781 - Manual (Page 1299)

25. Audio Codec Interface (HAC)
Rev.1.00 Jan. 10, 2008 Page 1269 of 1658
REJ09B0261-0100
25.3.1 Control and Status Register (HACCR)
HACCR is a 32-bit read/write register for controlling input/output and monitoring the interface
status.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
⎯ ⎯ ⎯ ⎯
Bit:
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Initial value:
R R R R R R R R R R R R R R R R
R R W R R R R R
R/W:
Bit:
Initial value:
R/W:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
R R R R W W R R
CR CDRT WMRT ST
0
Bit Bit Name
Initial
Value R/W Description
31 to 16
⎯ All
0 R Reserved
These bits are always read as 0. The write value should
always be 0.
15 CR 0 R Codec Ready
0: The HAC-connected codec is not ready.
1: The HAC-connected codec is ready.
14 to 12
⎯ All
0 R Reserved
These bits are always read as 0. Write prohibited.
11 CDRT 0 W HAC Cold Reset
Use a cold reset only after power-on, or only to exit
from the power-down mode by the power-down
command.
[Write]
0: Always write 0 to this bit before writing 1 again.
(When this bit is changed from 0 to 1, a cold reset is
performed.)
1: Performs a cold reset on the HAC-connected codec.
[Read]
Always read as 0.