Renesas SH7781 - Manual (Page 1389)

27. NAND Flash Memory Controller (FLCTL)
Rev.1.00 Jan. 10, 2008 Page 1359 of 1658
REJ09B0261-0100
27.3.9 Ready Busy Timeout Setting Register (FLBSYTMR)
FLBSYTMR is a 32-bit readable/writable register that specifies the timeout time when the FRB
pin is busy.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R R R R R R R R R R R R/W R/W R/W R/W R/W
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
RBTMOUT[20:16]
RBTMOUT[15:0]
Bit Bit Name
Initial
Value R/W Description
31 to 21 — All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
20 to 0 RBTMOUT[20:0] H'00000 R/W Ready Busy Timeout
Specify timeout time in the busy state
Set the timeout time in the busy state (with the clock
cycles of a peripheral clock)
When these bits are set to 0, timeout does not
occur.