Renesas SH7781 - Manual (Page 651)

13. PCI Controller (PCIC)
Rev.1.00 Jan. 10, 2008 Page 621 of 1658
REJ09B0261-0100
(21) PCI Memory Bank Mask Register 2 (PCIMBMR2)
This register is the mask register for PCIMBR2. This register specifies the memory space size on
the PCI bus for a memory read or write to the PCI memory space 2 by the CPU or DMAC.
See section 13.4.3 (2), Accessing PCI Memory Space.
SH R/W:
PCI R/W:
SH R/W:
PCI R/W:
16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 Bit:
Initial value:
R R R/W R/W
R R R R
R/W R/W R/W R/W
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
— — — — — — — — — — — — — — — —
— — — —
— — — —
— — — — — — — — — — — —
R R R R R R R R R R R R
R/W R/W R/W R/W R/W R R R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
— — — — — — — — — — — —
— — — — — MSBAM2
0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit:
Initial value:
Bit Bit Name
Initial
Value R/W
Description
31 to 29
⎯
All 0 SH: R
PCI:
⎯
Reserved
These bits are always read as 0. The write value
should always be 0.
28 to 18 MSBAM2 All 0 SH: R/W
PCI:
⎯
PCI Memory Space 2 Bank Address Mask (11 bits)
0 0000 0000 00: 256 kbytes
0 0000 0000 01: 512 kbytes
0 0000 0000 11: 1 Mbyte
0 0000 0001 11: 2 Mbytes
0 0000 0011 11: 4 Mbytes
0 0000 0111 11: 8 Mbytes
0 0000 1111 11: 16 Mbytes
0 0001 1111 11: 32 Mbytes
0 0011 1111 11: 64 Mbytes
0 0111 1111 11: 128 Mbytes
0 1111 1111 11: 256 Mbytes
1 1111 1111 11: 512 Mbytes
Other than above: Setting prohibited
17 to 0
⎯
All 0 SH: R
PCI:
⎯
Reserved
These bits are always read as 0. The write value
should always be 0.