Renesas SH7781 - Manual (Page 501)

12. DDR2-SDRAM Interface (DBSC2)
Rev.1.00 Jan. 10, 2008 Page 471 of 1658
REJ09B0261-0100
Access Size Address
MDQ31 to
MDQ24 MDQ23 to
MDQ16 MDQ15 to
MDQ8 MDQ7 to
MDQ0
Quadword Address 0
(First access:
address 4)
Data
63 to 56
Data
55 to 48
Data
47 to 40
Data
39 to 32
Address 0
(Second access:
Address 0)
Data
31 to 24
Data
23 to 16
Data
15 to 8
Data
7 to 0
Table 12.6 Data Alignment for Access in Big Endian when External Data Bus Width Is Set
to 32 Bits
Access Size Address
MDQ31 to
MDQ24 MDQ23 to
MDQ16 MDQ15 to
MDQ8 MDQ7 to
MDQ0
Byte Address 0 Data
7 to 0
Address 1 Data
7 to 0
Address 2 Data
7 to 0
Address 3 Data
7 to 0
Address 4 Data
7 to 0
Address 5 Data
7 to 0
Address 6 Data
7 to 0
Address 7 Data
7 to 0