Renesas SH7781 - Manual (Page 1491)

29. User Break Controller (UBC)
Rev.1.00 Jan. 10, 2008 Page 1461 of 1658
REJ09B0261-0100
Bit Bit Name
Initial
Value R/W
Description
23 to 16 AIV All 0 R/W ASID Specify
Specifies the ASID value to be included in the match
conditions.
15 DBE 0 R/W Data Value Enable* 3
Specifies whether or not to include the data value in the
match condition. This bit is valid only when the operand
access cycle is specified as a match condition.
0: The data value is not included in the match
conditions; thus, not checked.
1: The data value is included in the match conditions.
14 to 12 SZ All 0 R/W Operand Size Select
Specifies the operand size to be included in the match
conditions. This bit is valid only when the operand
access cycle is specified as a match condition.
000: The operand size is not included in the match
condition; thus, not checked (any operand size
specifies the match condition). *
1
001: Byte access
010: Word access
011: Longword access
100: Quadword access* 2
Others: Reserved (setting prohibited)
11 ETBE 0 R/W Execution Count Value Enable
Specifies whether or not to include the execution count
value in the match conditions. If this bit is 1 and the
match condition satisfaction count matches the value
specified by the CETR1 register, the operation specified
by the CRR1 register is performed.
0: The execution count value is not included in the
match conditions; thus, not checked.
1: The execution count value is included in the match
conditions.
10 to 8 — All 0 R Reserved
For read/write in this bit, refer to General Precautions
on Handling of Product.