Renesas SH7781 - Manual (Page 706)

14. Direct Memory Access Controller (DMAC)
Rev.1.00 Jan. 10, 2008 Page 676 of 1658
REJ09B0261-0100
14.3.2 DMA Source Address Registers B0 to B3, B6 to B9 (SARB0 to SARB3, SARB6 to
SARB9)
SARB are 32-bit readable/writable registers that specify the source address of a DMA transfer that
is set in SAR again in repeat/reload mode. The data written to SAR by the CPU is also written to
SARB. To set the address that is different from SAR address, write data to SAR, then, to SARB.
A word or longword boundary address should be specified when a word or longword transfer is
performed respectively. A 16-byte or 32-byte boundary value should be specified when a 16-byte
or 32-byte transfer is performed respectively.
The initial value of SARB is undefined.
16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
BIt:
Initial value:
R/W:
0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
BIt:
Initial value:
R/W: