Renesas SH7781 - Manual (Page 422)

11. Local Bus State Controller (LBSC)
Rev.1.00 Jan. 10, 2008 Page 392 of 1658
REJ09B0261-0100
Table 11.10 8-Bit External Device/Big-Endian Access and Data Alignment
Operation Data Bus Strobe Signals
Access
Size Address
No.
D31 to
D24 D23 to
D16 D15 to
D8 D7 to
D0
WE3 WE2 WE1 WE0
Byte n 1
⎯ ⎯ ⎯ Data
7 to 0
Asserted
2n 1
⎯ ⎯ ⎯ Data
15 to 8
Asserted Word
2n + 1 2
⎯ ⎯ ⎯ Data
7 to 0
Asserted
4n 1
⎯ ⎯ Data
31 to 24
Asserted
4n + 1 2
⎯ ⎯ ⎯ Data
23 to 16
Asserted
4n + 2 3
⎯ ⎯ ⎯ Data
15 to 8
Asserted
Longword
4n + 3 4
⎯ ⎯ ⎯ Data
7 to 0
Asserted
32 Bytes* 8n 1
⎯ ⎯ ⎯ Data
7
to 0
Asserted
8n + 1 2
⎯ ⎯ ⎯ Data
15
to 8
Asserted
8n + 2 3
⎯ ⎯ ⎯ Data
23
to 16
Asserted
… … … … … … … … … …
8n + 31 32 ⎯ ⎯ ⎯ Data
255 to
248
Asserted
Note: * This table shows an example when the access start address is on the 32-byte
boundary. When the start address is not on the 32-byte boundary, accesses are
performed up to immediately before the 32-byte boundary and the address is wrapped
around to the previous 32-byte boundary.