Delta RMC101 - Manual (Page 251)

Digital I/O 5.1
Communications 5-1
CPU: Independent
DI/O: Common high or low side
Logic polarity CPU: True High
DI/O: Configurable (True high default)
Isolation 2500 VAC RMS
Maximum voltage ±30 V (DC or peak AC)
Maximum current ±100 mA
Max. propagation
delay
1.5 ms
Logic 1 Low impedance (50 W maximum)
Logic 0 High impedance (<1 mA leakage current
at 250 V)
5.1.2 Digital I/O Wiring
Digital Outputs
The outputs from the Digital I/O’s are solid state relays (SSRs). When they are ”r;off” they have
high impedance, and when ”r;on” they have low impedance (50 W maximum, 25 W typical).
Because the outputs are isolated, the user must power them externally. The maximum current
and voltage for the outputs is 100 mA and 30 V.
5.1.2.1 CPU Digital Outputs
Each CPU digital output has a + and - connection. Both lines must be connected for the output to
function. Because both sides of the output are provided, the switches may be independently
connected in a high side or low side configuration (that is, with the load (input) on the source or
sinking side of the output). See the wiring diagrams below.
5.1.2.2 DI/O Digital Outputs
There are nine pins on the ”r;OUTPUTS” section of the Digital I/O. The bottom pin is marked ”r;Output
Cmn” and is common to one side of all the output relays. The other side of the eight SSRs are
numbered 0-7.
The switches can be wired in a high-side or low-side configuration. A high-side configuration ties
”r;Output Cmn” to the output power source; the SSRs control power to the load. A low-side
configuration ties ”r;Output Cmn” to GND.
Digital Output Wiring Diagrams
External Fuses should be used to protect the SSRs if there is a possibility of over-current. When
switching inductive loads, it is important to place a diode or tranzorb across the load to protect the
switch when transitioning from an ”r;on” to an ”r;off” state. Otherwise, the collapsing magnetic
field can cause a reverse voltage spike in excess of the 30 V rating of the SSR. See figures below