Register interface signals, 10gbase-kr phy register definitions, Register interface signals -32 – Altera Transceiver PHY IP Core User Manual
Page 88: 10gbase-kr phy register definitions -32
Signal Name
Direction
Description
rxeq_done
Input
Link training requires RX equalization to be
complete. Tie this signal to 1 to indicate that RX
equalization is complete.
Register Interface Signals
The Avalon-MM master interface signals provide access to all registers.
Refer to the Typical Slave Read and Write Transfers and Master Transfers sections in the Avalon Memory-
Mapped Interfaces chapter of the Avalon Interface Specifications for timing diagrams.
Table 4-18: Avalon-MM Interface Signals
Signal Name
Direction
Description
mgmt_clk
Input
The clock signal that controls the Avalon-MM PHY
management, interface. If you plan to use the same
clock for the PHY management interface and
transceiver reconfiguration, you must restrict the
frequency range to 100-125 MHz to meet the
specification for the transceiver reconfiguration
clock.
mgmt_clk_reset
Input
Resets the PHY management interface. This signal
is active high and level sensitive.
mgmt_addr[7:0]
Input
8-bit Avalon-MM address.
mgmt_writedata[31:0]
Input
Input data.
mgmt_readdata[31:0]
Output
Output data.
mgmt_write
Input
Write signal. Active high.
mgmt_read
Input
Read signal. Active high.
mgmt_waitrequest
Output
When asserted, indicates that the Avalon-MM slave
interface is unable to respond to a read or write
request. When asserted, control signals to the
Avalon-MM slave interface must remain constant.
Related Information
10GBASE-KR PHY Register Definitions
The Avalon-MM master interface signals provide access to the control and status registers.
The following table specifies the control and status registers that you can access over the Avalon-MM
PHY management interface. A single address space provides access to all registers.
4-32
Register Interface Signals
UG-01080
2015.01.19
Altera Corporation
Backplane Ethernet 10GBASE-KR PHY IP Core with Early Access FEC Option