Altera Transceiver PHY IP Core - Manual (Page 501)

Status Condition Protocol Mapping of Status Flags to RX Data Value
Deletion
Basic double width
Serial RapidIO double width
RXD[62:62] = rx_
rmfifostatus[1:0]
, or
RXD[46:45] = rx_rmfifos-
tatus[1:0]
, or
RXD[30:29] = rx_
rmfifostatus[1:0]
, or
RXD[14:13] = rx_rmfifos-
tatus[1:0]
2'b01
All other protocols Depending on the FPGA fabric to
PCS interface width either:
RXD[46:45] = rx_rmfifos-
tatus[1:0]
, or
RXD[14:13] = rx_rmfifos-
tatus[1:0]
2'b01
Related Information
Transceiver Architecture in Cyclone V Devices
Word Aligner and BitSlip Parameters
The word aligner aligns the data coming from RX PMA deserializer to a given word boundary. When the
word aligner operates in bitslip mode, the word aligner slips a single bit for every rising edge of the bit slip
control signal.
Note: For more information refer to the Word Aligner section in the Transceiver Architecture inCycloneV
Devices.
Table 15-14: Word Aligner and BitSlip Parameters
Parameter Range Description
Enable TX bit slip On/Off When you turn this option On, the PCS
includes the bitslip function. The outgoing TX
data can be slipped by the number of bits
specified by the
tx_bitslipboundarysel
control signal.
Enable tx_std_bitslipboundarysel
control input port.
On/Off When you turn this option On, the PCS
includes the optional
tx_std_bitslipboun-
darysel
control input port.
15-18 Word Aligner and BitSlip Parameters
UG-01080
2015.01.19
Altera Corporation Cyclone V Transceiver Native PHY IP Core Overview
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