Altera Transceiver PHY IP Core - Manual (Page 462)

Name Direction Description
rx_is_lockedtoref
[ -1:0]
Output When asserted, the CDR is locked to the
incoming reference clock.
rx_clkslip
[ -1:0]
Input When you turn this signal on, deserializer
performs a clock slip operation to achieve word
alignment. The clock slip operation alternates
between skipping 1 serial bit and pausing the
serial clock for 2 cycles to achieve word
alignment. As a result, the period of the parallel
clock could be extended by 2 unit intervals (UI)
during the clock slip operation. This is an
optional control input signal.
Reconfig Interface Ports
reconfig_to_xcvr
[( 70-1):0]
Input Reconfiguration signals from the Transceiver
Reconfiguration Controller. grows linearly
with the number of reconfiguration interfaces.
reconfig_from_xcvr
[( 46-1):0]
Output Reconfiguration signals to the Transceiver
Reconfiguration Controller. grows linearly
with the number of reconfiguration interfaces.
tx_cal_busy
[ -1:0]
Output When asserted, indicates that the initial TX
calibration is in progress. It is also asserted if
reconfiguration controller is reset. It will not be
asserted if you manually re-trigger the calibra‐
tion IP. You must hold the channel in reset
until calibration completes.
rx_cal_busy
[ -1:0]
Output When asserted, indicates that the initial RX
calibration is in progress. It is also asserted if
reconfiguration controller is reset. It will not be
asserted if you manually re-trigger the calibra‐
tion IP.
Table 14-39: Signal Definitions for tx_parallel_data with and without 8B/10B Encoding
The following table shows the signals within
tx_parallel_data
that correspond to data, control, and status
signals for a single 11-bit word. The
tx_parallel_data
bus is always 64 bits to enable reconfigurations between
the Standard and 10G PCS datapaths. If you only enable the Standard datapath, the 20, high-order bits are not
used.
TX Data Word Description
Signal Definitions with 8B/10B Enabled
tx_parallel_data[7:0]
TX data bus.
tx_parallel_data[8]
TX data control character.
tx_parallel_data[9]
Force disparity, validates disparity field.
UG-01080
2015.01.19
Common Interface Ports for Arria V GZ Native PHY 14-51
Arria V GZ Transceiver Native PHY IP Core Altera Corporation
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