Altera Transceiver PHY IP Core User Manual
Page 685
Date
Document
Version
Changes Made
Arria V Transceiver Native PHY
November 2012
1.8
• Added support for Standard datapath.
• Added support for multiple PLLs.
• Moved Analog Options to a separate chapter.
• Added constraint for
tx_digitalreset
when TX PCS uses
bonded clocks.
Arria V GZ Transceiver Native PHY
November 2012
1.8
• Initial release.
Cyclone V Transceiver Native PHY
November 2012
1.8
• Initial release.
Reconfiguration Controller
November 2012
1.8
• Added
MIF addressing mode
option. Byte and word (16 bits)
addressing are available.
• Added ATX PLL reference clock switching and reconfiguration
of ATX PLL settings, including counters.
• Added support for ATX PLL reconfiguration.
• Added statement that if you are using the EyeQ monitor when
DFE is enabled, if you must use the EyeQ monitor with a 1D-
eye.
• Corrected definition of
DFE_control
bit at 0xa. This register is
write only.
• Removed duty cycle calibration. This function is run automati‐
cally during the power-on sequence.
• Added DFE support including examples showing how to
program this function.
• Added DCD for Arria V devices.
• Updated data for writes in Streamer Mode 1 Reconfiguration.
• Changed data value to write in step 7 of Streamer-Based
Reconfiguration.
• Changed data value to write to setup streaming in Reconfigura‐
tion of Logical Channel 0 Using a MIF.
Transceiver PHY Reset Controller
November 2012
1.8
• Added Arria V GZ support.
• Added SDC constraint for
tx_digitalreset
when TX PCS
uses bonded clocks.
Analog Parameters Set Using QSF Assignments
UG-01080
2015.01.19
Revision History for Previous Releases of the Transceiver PHY IP Core
21-25
Additional Information for the Transceiver PHY IP Core
Altera Corporation