Xaui phy data interfaces, Xaui phy data interfaces -11, Figure 6-4 – Altera Transceiver PHY IP Core User Manual
Page 151
The following figure illustrates the top-level signals of the XAUI PHY IP Core for the soft IP implementa‐
tion for both the single and DDR rates.
Figure 6-4: XAUI Top-Level Signals—Soft PCS and PMA
xgmii_tx_dc[71:0]
xgmii_tx_clk
xmii_rx_dc[71:0]
xgmii_rx_clk
phy_mgmt_clk
phy_mgmt_clk_reset
phy_mgmt_write
phy_mgmt_read
phy_mgmt_waitrequest
pll_ref_clk
XAUI Top-Level Signals
Rx Status
Optional
xaui_rx_serial_data[3:0]
xaui_tx_serial_data[3:0]
rx_channelaligned
rx_disperr[7:0]
rx_errdetect[7:0]
rx_syncstatus[7:0]
rx_recovered_clk[3:0]
rx_ready
tx_ready
Transceiver
Serial Data
SDR TX XGMII
SDR RX XGMII
Avalon-MM PHY
Management
Interface
Clock
PMA
Channel
Controller
XAUI PHY Data Interfaces
The XAUI PCS interface to the FPGA fabric uses a SDR XGMII interface. This interface implements a
simple version of Avalon-ST protocol. The interface does not include ready or valid signals; consequently,
the sources always drive data and the sinks must always be ready to receive data.
For more information about the Avalon-ST protocol, including timing diagrams, refer to the Avalon
Interface Specifications.
Depending on the parameters you choose, the application interface runs at either 156.25 Mbps or 312.5
Mbps. At either frequency, data is only driven on the rising edge of clock. To meet the bandwidth require‐
ments, the datapath is eight bytes wide with eight control bits, instead of the standard four bytes of data
and four bits of control. The XAUI IP Core treats the datapath as two, 32-bit data buses and includes logic
to interleave them, starting with the low-order bytes.
Figure 6-5: Interleaved SDR XGMII Data Mapping
Interleaved Result
Original XGMII Data
[63:56]
[55:48]
[47:40]
[39:32]
[31:24]
[23:16]
[15:8]
[7:0]
[63:56]
[31:24]
[55:48]
[23:16]
[47:40]
[15:8]
[39:32]
[7:0]
UG-01080
2015.01.19
XAUI PHY Data Interfaces
6-11
XAUI PHY IP Core
Altera Corporation