Altera Transceiver PHY IP Core - Manual (Page 190)

Figure 8-1: Gen3 PCI Express PHY (PIPE) with Hard IP PCS and PMA in Arria V GZ and Stratix V GX
Devices
PHY IP Core for PCI Express - Gen3
Arria V GZ or Stratix V FPGA
PMA:
Analog Buffers
SERDES
10-bit Interface
Avalon-MM Cntrl & Status
Avalon-ST PIPE
to ASIC,
ASSP,
FPGA
PCIe
Link
Transceiver
Reconfiguration
Controller
Embedded
Controller
PCIe Transaction
Data Link
Physical Layers
(Soft Logic)
Reconfiguration to/from XCVR
PCS:
TX/RX Phase Comp FIFO
Encoder/Decoder
Scrambler/Descrambler
Gearbox
TX Bit Slip
Rate Match FIFO
Block Synchronization
Rx Detection
Auto Speed Negotiation
Figure 8-2: Gen1 and Gen2 PCI Express PHY (PIPE) with Hard IP PCS and PMA in Arria V GZ and Stratix V
GX Devices
PHY IP Core for PCI Express - Gen1 and Gen2
Arria V GZ or Stratix V GX
PCS:
TX/RX Phase Comp FIFO
Byte Serialzier/Deserializer
8B/10B
Rate Match FIFO
Word Aligner
PMA:
Analog Buffers
SERDES
10-bit Interface
Avalon-MM Cntrl & Status
Avalon-ST PIPE
to ASIC,
ASSP,
FPGA
PCIe
Link
Transceiver
Reconfiguration
Controller
Embedded
Controller
Reconfiguration to/from XCVR
PCIe Transaction
Data Link
Physical Layers
(Soft Logic)
For more detailed information about the PCI Express PHY PIPE transceiver channel datapath, clocking,
and channel placement, refer to the “PCI Express” section in the in the Transceiver Configurations in
Arria V GZ Devices or Transceiver Configurations in Stratix V Devices as appropriate.
Related Information
• Intel PHY I nterface for PCI Express (PIPE) Architecture PCI Express 2.0
• PHY Interface for the PCI Express Architecture PCI Express 3.0
8-2 PHY IP Core for PCI Express (PIPE)
UG-01080
2015.01.19
Altera Corporation PHY IP Core for PCI Express (PIPE)
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