Altera Transceiver PHY IP Core User Manual
Page 663
Chapter
Document
Version
Changes Made
Custom PHY IP Core 2.7
Made the following changes:
• Updated the chapter to indicate new IP instantiation flow using
the IP Catalog.
• Changed the device family support to final for this IP core in
Table 9-1: Device Family Support.
• Changed the description of
tx_bitslipboundaryselect
signal
in Optional Status Interfaces section.
• Changed the word alignment pattern for Ethernet in Table 9-11:
Presets for Ethernet Protocol.
• Added a note related to compile warning (12020) in the descrip‐
tion of
tx_analogreset
signal.
• Corrected byte ordering pattern length for configuration 4 in
Byte Order Parameters section.
Low Latency PHY IP
Core
2.7
Made the following changes:
• Updated the chapter to indicate new IP instantiation flow using
the IP Catalog.
• Changed the device family support fo final for this IP core in
Table 10-1: Device Family Support.
Deterministic Latency
PHY IP Core
2.7
Made the following changes:
• Updated the chapter to indicate new IP instantiation flow using
the IP Catalog.
• Changed the device family support fo final for this IP core in
Table 11-4: Device Family Support.
• Updated Table: PMA Datapath Total Latency with actual
hardware delays.
• Removed description and figure related to using PLL feedback
method to align the TX core clock with the RX core clock.
• In Deterministic Latency PHY Delay Estimation Logic section:
• Added description of
rx_std_bitslipboundaryselect
signal.
• Added footnotes related to latency calculations in Table 11-2
and Table 11-3.
UG-01080
2015.01.19
Additional Information for the Transceiver PHY IP Core
21-3
Additional Information for the Transceiver PHY IP Core
Altera Corporation