Altera Transceiver PHY IP Core - Manual (Page 317)

When you enable the simplified data interface and enable the rate match FIFO status ports, the rate match
FIFO bits map to the high-order bits of the data bus as listed in the following table. This table uses the
following definitions:
• Basic double width: The Standard PCS protocol mode GUI option is set to basic. The FPGA data
width is twice the PCS data width to allow the fabric to run at half the PCS frequency.
• Serial TM RapidIO double width: You are implementing the Serial RapidIO protocol. The FPGA data
width is twice the PCS data width to allow the fabric to run at half the PCS frequency.
Note: If you have the auto-negotiation state machine in your transceiver design, please note that the rate
match FIFO is capable of inserting or deleting the first two bytes (K28.5//D2.2) of /C2/ ordered sets
during auto-negotiation. However, the insertion or deletion of the first two bytes of /C2/ ordered
sets can cause the auto-negotiation link to fail. For more information, visit Altera Knowledge Base
Support Solution .
Table 12-16: Status Flag Mappings for Simplified Native PHY Interface
Status Condition Protocol Mapping of Status Flags to RX Data Value
Full
PHY IP Core for PCI
Express (PIPE)
Basic double width
RXD[62:62] = rx_
rmfifostatus[1:0]
, or
RXD[46:45] = rx_rmfifos-
tatus[1:0]
, or
RXD[30:29] = rx_
rmfifostatus[1:0]
, or
RXD[14:13] = rx_rmfifos-
tatus[1:0]
2'b11 = full
XAUI, GigE, Serial RapidIO
double width
rx_std_rm_fifo_full 1'b1 = full
All other protocols Depending on the FPGA fabric to
PCS interface width either:
RXD[46:45] = rx_rmfifos-
tatus[1:0]
, or
RXD[14:13] = rx_rmfifos-
tatus[1:0]
2'b11 = full
UG-01080
2015.01.19
Standard PCS Parameters for the Native PHY 12-19
Stratix V Transceiver Native PHY IP Core Altera Corporation
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