1588 delay requirements, 10gbase-r phy timequest timing constraints, 1588 delay requirements -30 – Altera Transceiver PHY IP Core User Manual
Page 54: 10gbase-r phy timequest timing constraints -30
1588 Delay Requirements
The 1588 protocol requires symmetric delays or known asymmetric delays for all external connections.
In calculating the delays for all external connections, you must consider the delay contributions of the
following elements:
• The PCB traces
• The backplane traces
• The delay through connectors
• The delay through cables
Accurate calculation of the channel-to-channel delay is important in ensuring the overall system accuracy.
10GBASE-R PHY TimeQuest Timing Constraints
The timing constraints for Stratix IV GT designs are in alt_10gbaser_phy.sdc. If your design does not
meet timing with these constraints, use LogicLock
™
for the
alt_10gbaser_pcs block
. You can also
apply LogicLock to the
alt_10gbaser_pcs
and slightly expand the lock region to meet timing.
The following example provides the Synopsys Design Constraints file (.sdc) timing constraints for the
10GBASE-R IP Core when implemented in a Stratix IV device. To pass timing analysis, you must
decouple the clocks in different time domains. Be sure to verify the each clock domain is correctly
buffered in the top level of your design. You can find the .sdc file in your top-level working directory. This
is the same directory that includes your top-level .v or .vhd file.
Example 3-3: Synopsys Design Constraints for Clocks
#**************************************************************
# Timing Information
#**************************************************************
set_time_format -unit ns -decimal_places 3
#**************************************************************
# Create Clocks
#**************************************************************
create_clock -name {xgmii_tx_clk} -period 6.400 -waveform { 0.000 3.200 }
[get_ports {xgmii_tx_clk}]
create_clock -name {phy_mgmt_clk} -period 20.00 -waveform { 0.000 10.000 }
[get_ports {phy_mgmt_clk}]
create_clock -name {pll_ref_clk} -period 1.552 -waveform { 0.000 0.776 }
[get_ports {ref_clk}]
#derive_pll_clocks
derive_pll_clocks -create_base_clocks
#derive_clocks -period "1.0"
# Create Generated Clocks
#**************************************************************
create_generated_clock -name pll_mac_clk -source [get_pins -compati-
bility_mode {*altpll_component|auto_generated|pll1|clk[0]}]
create_generated_clock -name pma_tx_clk -source [get_pins -compati-
bility_mode {*siv_alt_pma|pma_direct|auto_generated|transmit_pcs0|clkout}]
**************************************************************
## Set Clock Latency
#**************************************************************
#**************************************************************
# Set Clock Uncertainty
#**************************************************************
#**************************************************************
derive_clock_uncertainty
3-30
1588 Delay Requirements
UG-01080
2015.01.19
Altera Corporation
10GBASE-R PHY IP Core