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Altera Transceiver PHY IP Core User Manual

Page 312

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Table 12-11: General and Datapath Parameters

The following table describes the general and datapath options for the Standard PCS.

Parameter

Range

Description

Standard PCS protocol mode

basic

cpri

gige

srio_2p1

Specifies the protocol that you intend to

implement with the Native PHY. The

protocol mode selected guides the

MegaWizard in identifying legal settings for

the Standard PCS datapath. Use the following

guidelines to select a protocol mode:
basic -select this mode for when none of

the other options are appropriate. You

should also select this mode to enable

diagnostics, such as loopback.

cpri select this mode if you intend to

implement CPRI or another protocol that

requires deterministic latency. Altera

recommends that you select the

appropriate CPRI preset for the CPRI

protocol.

gige -select this mode if you intend to

implement Gigabit Ethernet. Altera

recommends that you select the

appropriate GIGE preset for the Ethernet

bandwidth you intend to implement.

srio_2p1 -select this mode if you intend to

implement the Serial RapidIO protocol.

Standard PCS/PMA interface width

8, 10, 16,

20, 32, 40

64, 80

Specifies the width of the datapath that

connects the FPGA fabric to the PMA. The

transceiver interface width depends upon

whether you enable 8B/10B. To simplify

connectivity between the FPGA fabric and

PMA, the bus bits used are not contiguous for

16- and 32-bit buses. 16-, 32-, and 64-bit

buses. Refer to

Table 12-10

for the bits used.

FPGA fabric/Standard TX PCS

interface width

8, 10, 16, 20 Shows the FPGA fabric to TX PCS interface

width which is calculated from the Standard

PCS/PMA interface width.

FPGA fabric/Standard RX PCS

interface width

8, 10, 16, 20 Shows the FPGA fabric to RX PCS interface

width which is calculated from the Standard

PCS/PMA interface width.

Enable Standard PCS low latency mode

On/ Off

When you turn this option On, all PCS

functions are disabled. This option creates a

the lowest latency Native PHY that allows

dynamic reconfigure between multiple PCS

datapaths.

12-14

Standard PCS Parameters for the Native PHY

UG-01080

2015.01.19

Altera Corporation

Stratix V Transceiver Native PHY IP Core

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