Altera Transceiver PHY IP Core - Manual (Page 42)

Table 3-13: 10GBASE-R Status, 1588, and PLL Reference Clock Outputs
Signal Name Direction Description
rx_block_lock
Output Asserted to indicate that the block synchron‐
izer has established synchronization.
rx_hi_ber
Output Asserted by the BER monitor block to
indicate a Sync Header high bit error rate
greater than 10 -4 .
rx_recovered_clk[:0]
Output This is the RX clock, which is recovered from
the received data stream.
pll_locked
Output When asserted, indicates that the TX PLL is
locked.
IEEE 1588 Precision Time Protocol
rx_latency_adj_10g [15:0]
Output When you enable 1588, this signal outputs
the real time latency in XGMII clock cycles
(156.25 MHz) for the RX PCS and PMA
datapath for 10G mode. Bits 0 to 9 represent
the fractional number of clock cycles. Bits 10
to 15 represent the number of clock cycles.
tx_latency_adj_10g [15:0]
Output When you enable 1588, this signal outputs
real time latency in XGMII clock cycles
(156.25 MHz) for the TX PCS and PMA
datapath for 10G mode. Bits 0 to 9 represent
the fractional number of clock cycles. Bits 10
to 15 represent the number of clock cycles.
PLL Reference Clock
pll_ref_clk
Input For Stratix IV GT devices, the TX PLL
reference clock must be 644.53125 MHz. For
Arria V and Stratix V devices, the TX PLL
reference clock can be either 644.53125 MHz
or 322.265625 MHz.
Optional Reset Control and Status Interface
This topic describes the signals in the optional reset control and status interface. These signals are
available if you do not enable the embedded reset controller.
Table 3-14: Avalon-ST RX Interface
Signal Name Direction Description
pll_powerdown
Input When asserted, resets the TX PLL.
3-18 Optional Reset Control and Status Interface
UG-01080
2015.01.19
Altera Corporation 10GBASE-R PHY IP Core
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