Altera Transceiver PHY IP Core - Manual (Page 580)

Related Information
• Transceiver Reset Control in Arria V Devices
• Transceiver Reset Control in Cyclone V Devices
• Transceiver Reset Control in Stratix V Devices
Device Family Support for Transceiver PHY Reset Controller
This section describes the transceiver PHY reset controller IP core device family support.
IP cores provide either final or preliminary support for target Altera device families. These terms have the
following definitions:
• Final support—Verified with final timing models for this device.
• Preliminary support—Verified with preliminary timing models for this device.
Table 17-1: Device Family Support
This table lists the level of support offered by the Transceiver PHY Reset Controller IP core for Altera device
families.
Device Family Support
Cyclone V devices Final
Arria V devices Final
Arria V GZ Final
Stratix V devices Final
Other device families No support
Performance and Resource Utilization for Transceiver PHY Reset
Controller
This section describes the performance and resource utilization for the transceiver PHY reset controller.
Table 17-2: Reset Controller Resource Utilization—Stratix V Devices
This table lists the typical expected device resource utilization, rounded to the nearest 50, for two configurations
using the current version of the Quartus II software targeting a Stratix V GX device. The numbers are rounded to
the nearest 50.
Configuration Combinational ALUTs Logic Registers
Single channel 50 50
4 channels, shared TX reset, separate
RX resets
100 150
UG-01080
2015.01.19
Device Family Support for Transceiver PHY Reset Controller 17-3
Transceiver PHY Reset Controller IP Core Altera Corporation
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