Altera Transceiver PHY IP Core - Manual (Page 326)

Offset OffsetBits R/W Name Description
0xA3 [15:0] R/W
Word Aligner Pattern
[15:0]
Stores the least significant 16 bits
from the word aligner pattern as
specified in the previous table.
0xA4 [15] R/W
Sync State Machine
Disable
Disables the synchronization state
machine. When the PCS-PMA Width
is 8 or 10, the value must be 1. When
the PCS-PMA Width is 16 or 20, the
value must be 0.
0xA6 [5] R/W
Auto Byte Align Disable
Auto aligns the bytes. Must be set to
1'b0 to enable the PRBS verifier.
0xB8 [13] R/W
DW Sync State Machine
Enable
Enables the double width state
machine. Must be set to 1'b0 to enable
the PRBS verifier.
0xB9 [11] R/W
Deterministic Latency
State Machine Enable
Enables a deterministic latency state
machine. Must be set to 1'b0 to enable
the PRBS verifier.
0xB
A
[11] R/W
Clock Power Down RX
When set to 1'b, powers down the
PRBS clock in the receiver.
12-28 Standard PCS Pattern Generators
UG-01080
2015.01.19
Altera Corporation Stratix V Transceiver Native PHY IP Core
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