Altera Transceiver PHY IP Core - Manual (Page 695)

Date Document
Version
Changes Made
November 2011 1.3
• Added MIF support to allow transceiver reconfiguration from
a .mif file that may contain updates to multiple settings.
• Added support for the following features:
• EyeQ
• AEQ
• ATX tuning
• PLL reconfiguration
• DC gain and four-stage linear equalization for the RX channels
• Removed Stratix IV device support.
• Changed frequency range of
phy_mgmt_clk
to 100-125 MHz.
All Chapters
July 2011 1.2.1
• Restricted frequency range of the
phy_mgmt_clk
to 90–100 MHz
for the Transceiver Reconfiguration Controller IP Core chapter.
There is no restriction on the frequency of
phy_mgmt_clk
for
Stratix V devices in the 10GBASE-R, XAUI, Interlaken, PHY IP
Core for PCI Express, Custom, and Low Latency PHYs;
however, to use the same clock source for both, you must restrict
this clock to 90–100 MHz.
• Added column specifying availability of read and write access for
PMA analog controls in the Transceiver Reconfiguration
Controller IP Core chapter.
• Renamed Avalon-MM bus in for Transceiver Reconfiguration
Controller
reconfig_mgmt*
.
• Provided frequency range for
phy_mgmt_clk
for the XAUI PHY
IP Core in Arria II GX, Cyclone IV GX, HardCopy IV, and
Stratix IV GX devices.
• Added register descriptions for the automatic reset controller to
the Low Latency PHY IP Core chapter.
• Added two steps to procedure to reconfigure a PMA control in
the Transceiver Reconfiguration Controller chapter.
• Corrected RX equalization DC gain in Transceiver Reconfigura‐
tion Controller chapter. It should be 0–4.
• Corrected serialization factor column in Low Latency PHY IP
Core chapter.
Introduction
UG-01080
2015.01.19
Revision History for Previous Releases of the Transceiver PHY IP Core 21-35
Additional Information for the Transceiver PHY IP Core Altera Corporation
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